First-in-first-out (FIFO) memories permit a user to synchronize communication between two different clock domains. Data words enter a FIFO memory through a write port synchronized to a write clock. Retrieved data words from the FIFO memory leave the FIFO memory through a read port synchronized to a read clock. In a conventional FIFO memory, the data words have the same width (number of bits in each word) at both the read and write ports. Should all the deposited data have been retrieved through the read port, the FIFO memory asserts an empty flag to prevent further read operations. Conversely, should all memory locations in the FIFO memory contain un-retrieved data words, the FIFO memory asserts a full flag to prevent further write operations.
Although the read and write ports of a conventional FIFO memories are generally the same width, they may be adapted to accommodate read and write ports of differing data widths. For example, a user may write 8-bit words into a FIFO memory and read 32-bit words from this same FIFO memory. Such use of a FIFO memory has proven to be problematic because each FIFO memory typically has a predetermined width, i.e., it is configured to store words of a given number of bits. For instance, consider as shown in FIG. 1 a FIFO memory 10 having a read port data width and a write port data width of 32 bits being used to coordinate communication between a write domain of 8-bit words and a read domain of 32 bits words. Given that FIFO memory 10 has a 32-bit read and write port data width, four 8-bit words received at FIFO memory 10 must be packaged into a single 32-bit word before they can be written into FIFO memory 10. To accommodate this packaging, four 8-bit registers 15 store the in-coming 8-bit words as controlled by a 1:4 de-multiplexer 20. Control logic 24 controls 1:4 de-multiplexer 20 to load registers 15 in the correct order. The FIFO memory write port (illustrated as four 8-bit ports 32) must then receive data words at 1/4 the rate of the write clock 25. This ¼write clock rate creates a third clock domain 35 for FIFO memory 10 in addition to the conventional write clock 25 and read clock 30. The requirement of this third clock domain complicates the design and implementation and slows performance of the resulting FIFO memory. In particular, additional programmable logic is usually necessary to coordinate flag generation, write counting and decoding, thereby increasing cost and complexity of the resulting FIFO memory.